RISC-V assembly language

RISC-V assembly language represents instructions from the RISC-V instruction set architecture in symbolic form. The base integer instruction set uses load-store operations: arithmetic works on registers, while memory is accessed explicitly with instructions such as lw, ld, sw, and sd.¹ A typical instruction has an operation followed by operands, as in add x5, x6, x7, although the exact accepted syntax depends on the assembler.

RISC-V defines thirty-two integer registers in the standard register convention, with x0 hard-wired to zero and registers such as x1 commonly serving as the return-address register. ABI names—including sp for the stack pointer, ra for the return address, and a0–a7 for argument and result registers—make source code more readable without changing the underlying register numbers.² Immediate operands are encoded within instructions, so larger constants generally require multiple instructions or assembler expansion.

RISC-V assemblers distinguish architectural instructions from pseudoinstructions that expand into one or more real instructions. For example, li loads an immediate, mv copies a register, nop encodes an inert operation, and ret commonly expands to an indirect jump through ra.³ Pseudoinstructions improve readability, but code that requires exact instruction selection must use the underlying architectural forms.

GNU as, usually invoked through GCC, accepts RISC-V assembly in source files and emits relocatable object files; LLVM provides a separate assembler and compiler toolchain with compatible architectural goals.³⁴

Source files also contain directives such as .text, .data, .globl, .section, .align, and .word. These are instructions to the assembler or linker rather than CPU operations. Labels name addresses, and branch or jump targets are normally written as labels so the toolchain can calculate encodings and relocations.

Portable RISC-V assembly depends on both the selected ISA extensions and the application binary interface. A target might combine a base such as RV64I with extensions for multiplication and division (M), atomics (A), single- and double-precision floating point (F and D), or compressed 16-bit instructions (C). The canonical ISA string communicates these capabilities to assemblers, compilers, linkers, and operating systems.¹

The RISC-V ELF psABI specifies calling conventions, register preservation, stack alignment, object-file conventions, and relocation behavior.⁵ A conventional function receives scalar arguments in a0–a7, returns values in a0 and a1, and preserves registers designated callee-saved. Assembly that calls C must follow the same ABI, including stack discipline and any required save and restore operations.

Address formation often uses auipc together with an addition or load, while symbolic references may receive relocations resolved only during linking. Position-independent code and thread-local storage therefore involve more than simple label substitution.

RISC-V assembly has several less visible layers that affect correctness and portability. The F and D extensions add floating-point registers and instructions, but their use also depends on ABI variants describing how floating-point values cross function interfaces.⁵ The compressed extension can reduce code size by selecting 16-bit encodings, yet the assembler—not the programmer alone—decides whether a suitable compressed form is emitted.

Assembler relaxation is another important edge case: toolchains may replace longer instruction sequences with shorter ones or transform address calculations after more information becomes available. This can make hand-counted instruction distances unreliable unless relaxation is controlled.³ The RISC-V ecosystem also permits vendor and experimental extensions, whose mnemonics and encodings are not necessarily portable across processors.

Finally, assembly source can target bare-metal firmware, an operating-system kernel, or user-space ELF programs. The same ISA instructions may therefore sit beneath very different environments, including startup code that initializes a stack and trap vector before any language runtime exists.

ISA

Instruction set architecture: the programmer-visible specification of instructions, registers, encodings, and architectural behavior.

ABI

Application binary interface: conventions governing binary compatibility, including calling conventions, register use, stack layout, and object files.

Pseudoinstruction

An assembler-supported mnemonic that expands into one or more architectural instructions.

Relocation

A linker-recorded adjustment that resolves a symbolic address or value when object files are combined.

ISA extension

An optional standardized or nonstandard addition to a RISC-V base instruction set.