NAND gate

A NAND gate produces the complement of an AND result. For inputs A and B, the Boolean expression is Y = ¬(A · B), also written Y = (A ∧ B)'. The output is therefore 0 only for A = 1 and B = 1; all other input combinations produce 1.¹

The same principle extends to three or more inputs: the output becomes low only when every input is high. A NAND gate is thus an inverted conjunction, whereas a NOR gate is an inverted disjunction.

NAND gates can construct every ordinary Boolean operation, which makes NAND a functionally complete, or universal, gate. A single NAND gate with its inputs tied together acts as a NOT gate: ¬A = A NAND A. Inverting the output of a NAND arrangement produces an AND function, while De Morgan's laws allow NAND-only constructions of OR and more complex networks.

For example, an OR gate can be made by NANDing the separately inverted inputs: A OR B = (A NAND A) NAND (B NAND B). From these elementary forms, designers can build adders, multiplexers, latches, decoders, and processors. Universal-gate design can reduce the number of distinct component types, although a circuit optimized exclusively for NAND may require more gates or have greater delay than a mixed-logic design.²

Physical NAND gates are built from transistors whose arrangement realizes an AND condition followed by inversion. In complementary metal–oxide–semiconductor (CMOS) logic, the pull-down network uses series n-channel transistors, while the pull-up network uses parallel p-channel transistors; this arrangement makes the output low when all inputs are high.³

Real gates have propagation delay, finite voltage thresholds, limited output drive, and power consumption. A datasheet specifies parameters such as supply-voltage range, input leakage, output current, transition time, and noise margins. Unused CMOS inputs should not be left floating because an indeterminate voltage can cause excess current or unpredictable switching; they are normally tied to a defined logic level.⁴

NAND logic is central to memory as well as combinational computation. Cross-coupled NAND gates can form an SR latch, allowing a circuit to retain one bit of state, while larger networks of NAND-derived gates implement registers and control logic. The same gate can also serve as a simple oscillator or pulse-shaping element when feedback and intentional delays are introduced, though such circuits require careful timing analysis.

At the transistor level, NAND and NOR are not equally economical in every technology. CMOS NAND gates generally place series devices in the pull-down path, so increasing the input count can increase resistance and delay; wide gates are consequently often decomposed into smaller stages. In standard-cell libraries, NAND gates appear in several drive strengths and sizes, allowing synthesis tools to balance area, speed, leakage, and fan-out.³ The symbol is commonly an AND-gate shape with an inversion bubble at its output.

Boolean algebra

An algebraic system for representing logical values and operations such as AND, OR, and NOT.

Universal gate

A logic gate from which any Boolean function can be constructed.

CMOS

Complementary metal–oxide–semiconductor, a transistor technology widely used for integrated digital logic.

Propagation delay

The time between an input transition and the corresponding output transition.

Noise margin

The voltage tolerance separating valid logic levels from unreliable interpretation.