Cache coherence

Cache coherence ensures that processors observe a suitably coordinated value for each shared memory location despite private caches. A cache may hold a clean copy that matches main memory, or a modified copy whose newer value must eventually become visible to the rest of the system. The usual unit is a cache line, commonly tens of bytes long, so unrelated words in the same line can be affected by one coherence transaction.

Coherence does not by itself specify the order in which reads and writes to different locations become visible. That broader contract is supplied by a memory-consistency model, such as the models defined for particular processor architectures. A coherent but weakly ordered machine can therefore preserve each location's single-writer history while still allowing some operations to appear reordered to software.

Coherence protocols coordinate caches by assigning states to each cache line and exchanging requests when a processor reads or writes it. In the widely taught MESI protocol, a line can be Modified, Exclusive, Shared, or Invalid; variants add states such as Owned or Forward to reduce unnecessary memory traffic. A write normally requires exclusive ownership, causing other valid copies to be invalidated or otherwise superseded.

Snooping protocols let caches observe a shared interconnect and react to transactions, which works naturally for smaller multiprocessors. Directory protocols record which caches hold a line and send targeted messages rather than broadcasting to every cache. Directory tracking scales better, but directories consume storage and introduce additional controller and network activity.¹

Coherence improves the programming model but can become a major source of latency and bandwidth demand. A read miss may fetch a line from another processor's cache, while a write to a shared line can repeatedly invalidate or transfer ownership among cores. The resulting pattern, called false sharing, occurs when independent variables occupy one cache line and can cause severe slowdowns even though the variables are logically unrelated.

Hardware counters commonly expose coherence-related events such as invalidations, snoop responses, cache-to-cache transfers, and ownership requests. Software reduces these costs through data placement, padding, read-mostly structures, and synchronization that limits unnecessary contention. Atomic operations and locks also depend on the architecture's memory-ordering rules; coherence alone is not a substitute for correct synchronization.

Coherence is not limited to conventional CPU caches: accelerators, input-output devices, and nonuniform memory systems may participate through hardware-coherent links or may require explicit cache maintenance. The cache-coherent NUMA model preserves a shared address space while making access time depend on which socket owns or supplies a line.²

Inclusive, exclusive, and non-inclusive cache hierarchies make different trade-offs in directory storage and eviction behavior. Evicting a line from an inclusive last-level cache can require invalidating copies in private caches, whereas a non-inclusive hierarchy may retain them. Coherence traffic can also reveal access patterns, making shared-cache behavior relevant to side-channel research as well as to performance engineering.

Cache line

The fixed-size block transferred and tracked by a cache-coherence protocol.

False sharing

Performance degradation caused when processors modify different words within the same coherence-tracked cache line.

Snooping

A coherence method in which caches observe transactions on a shared interconnect.

Directory protocol

A protocol that records the caches holding a line and directs coherence messages to them.

Memory consistency

The architectural rules governing the ordering and visibility of memory operations, distinct from per-location coherence.