Other meanings of Arithmetic logic unit
COMPUTER ARCHITECTURE
An arithmetic logic unit (ALU) is a digital circuit performing arithmetic and bitwise operations in a processor. It receives operand values and control signals, produces a result, and commonly reports status conditions such as carry, zero, negative, or overflow. An ALU is a central execution component, although modern processors often contain several specialized units alongside it.1
The ALU combines operand selection, Boolean logic, binary addition, and result selection into one execution datapath. Multiplexers choose inputs, a control field selects the operation, and combinational circuits calculate the output from the current inputs. Typical operations include addition, subtraction, conjunction, disjunction, exclusive OR, comparison, and shifts. A processor's control unit decodes an instruction and supplies the ALU with the operation code and operand-routing signals.1
Subtraction is commonly implemented with the same adder used for addition: one operand is complemented and a carry-in is asserted, producing two's-complement subtraction. Comparisons may be performed by subtracting operands and examining the result or its flags rather than by requiring a wholly separate arithmetic circuit.
An ALU's result width usually matches the processor's datapath width, but its internal carry path and outputs can be wider or differently organized. A carry flag records an unsigned carry out, while an overflow flag identifies a signed result outside the representable range; these conditions are distinct. Zero and negative indicators are often derived from the result bits.2
Most ALUs are combinational: they calculate a value while inputs and controls remain stable, and a clocked register captures that value later in the pipeline. The longest logic path influences the processor's clock period. Faster adders, such as carry-lookahead or prefix designs, reduce carry-propagation delay at the cost of area and wiring. Instruction sets differ in whether ordinary arithmetic updates flags automatically, optionally, or not at all.
The ALU is one stage in a larger datapath rather than a complete processor. Registers or a register file provide operands, the ALU computes, and a write-back path stores the result; the control and status logic coordinates these transfers. In a pipelined CPU, several instructions can occupy different stages simultaneously, while forwarding and hazard-control mechanisms handle dependencies between results and later operands.3
Processors frequently replicate ALUs or pair them with specialized units. A floating-point unit handles floating-point arithmetic, and vector or SIMD units apply operations to multiple packed elements. Address-generation units may resemble small integer ALUs but are dedicated to calculating memory addresses. In simple microcontrollers, one ALU may serve nearly every integer instruction; in superscalar processors, several execution ports can accept independent ALU work in the same cycle.
Many operations associated with an ALU are implemented through reuse rather than separate arithmetic blocks. Logical operations can be selected bit by bit with simple gates, while variable shifts may use a barrel shifter or a sequence of staged multiplexers. A comparison instruction can discard the subtraction result and retain only a Boolean condition, and a conditional move can use that condition to select between two already computed values.
ALU behavior also exposes architectural edge cases. Fixed-width arithmetic wraps modulo a power of two when overflow is ignored, whereas signed overflow is interpreted through a separate condition. Some instruction sets provide saturating arithmetic for multimedia or signal-processing workloads, preventing wraparound at the numeric limits. Educational designs such as the Nand2Tetris ALU make these choices explicit by deriving arithmetic and logical functions from elementary gates.4 The precise flags, widths, shift rules, and exceptional cases remain properties of an instruction set architecture, not universal features of every ALU.5
Terminology and exact flag behavior vary among instruction set architectures; the description here concerns the general processor component.
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